1 january 2001 hm-6617/883 2k x 8 cmos prom features this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. low power standby and operating power - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 a - iccop . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma at 1mhz fast access time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns industry standard pinout single 5.0v supply cmos/ttl compatible inputs high output drive . . . . . . . . . . . . . . . . 12 lsttl loads synchronous operation on-chip address latches separate output enable operating temperature range . . . . . . -55 o c to +125 o c description the hm-6617/883 is a 16,384-bit fuse link cmos prom in a 2k word by 8-bit/word format with ?hree-state outputs. this prom is available in the standard 0.600 inch wide 24 pin sbdip, the 0.300 inch wide slim sbdip, and the jedec standard 32 pad clcc. the hm-6617/883 utilizes a synchronous design technique. this includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. this design technique, combined with the intersil advanced self-aligned silicon gate cmos process technology offers ultra-low standby current. low iccsb is ideal for battery applications or other systems with low power requirements. the intersil nicr fuse link technology is utilized on this and other intersil cmos proms. this gives the user a prom with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. nicr fuse technology combined with the low power characteristics of cmos provides an excellent alternative to standard bipolar proms or nmos eproms. all bits are manufactured storing a logical ? and can be selectively programmed for a logical ??at any bit location. ordering information package temperature range 90ns 120ns package no. sbdip -55 o c to +125 o c hm1-6617b/883 hm1-6617/883 d24.6 slim sbdip -55 o c to +125 o c hm6-6617b/883 hm6-6617/883 d24.3 clcc -55 o c to +125 o c hm4-6617b/883 hm4-6617/883 j32.a pinouts hm-6617/883 (sbdip) top view hm-6617/883 (clcc) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd v cc a9 p g a10 q7 q5 q4 q3 a8 e q6 5 6 7 8 11 10 9 13 12 27 28 29 26 25 24 23 22 21 3 2 1 4 32 31 30 16 17 18 19 20 14 15 a6 a5 a4 a3 a2 a1 a0 nc q0 q1 q2 gnd nc q3 q4 q5 v cc nc nc a7 nc nc nc a8 a9 nc g a10 e q7 q6 p pin description pin description nc no connect a0-a10 address inputs e chip enable q data output v cc power (+5v) g output enable p (note) program enable note: p should be hardwired to v cc except during programming. file number 3016.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 2001
2 functional diagram latched address register gated row decoder 16 128 x 128 matrix 128 7 7 a a e a g g a10 a9 a7 a8 a6 a5 a4 msb l latched address register a0 a1 a2 a3 gated column decoder and data output control 4 l msb lsb lsb 16 16 16 16 16 16 16 a 4 g address latches and gated decoders: gate on falling edge of g latch on falling edge of e all lines positive logic: active high a high output active three-state buffers: 8 q0 q1 q2 q3 q4 q5 q6 q7 hm-6617/883
3 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.3v to vcc +0.3v typical derating factor . . . . . . . . . . . . 5ma/mhz increase in iccop esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.8v input high voltage . . . . . . . . . . . . . . . . . . . . . . +2.4v to vcc +0.3v thermal resistance ja jc sbdip package . . . . . . . . . . . . . . . . . . 48 o c/w 9 o c/w slim sbdip . . . . . . . . . . . . . . . . . . . . . 65 o c/w 14 o c/w clcc package . . . . . . . . . . . . . . . . . . 58 o c/w 19 o c/w maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 gates caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. table 1. hm-6617/883 dc electrical performance specifications device guaranteed and 100% tested parameter symbol (notes 1, 4) conditions group a subgroups temperature limits units min max high level output voltage voh1 vcc = 4.5v, io = -2.0ma 1, 2, 3 -55 o c ta +125 o c 2.4 - v low level output voltage vol vcc = 4.5v, io = +4.8ma 1, 2, 3 -55 o c ta +125 o c - 0.4 v high impedance output leakage current iioz vcc = 5.5v, g = 5.5v, vi/o = gnd or vcc 1, 2, 3 -55 o c ta +125 o c -1.0 1.0 a input leakage current ii vcc = 5.5v, vi = gnd or vcc, p not tested 1, 2, 3 -55 o c ta +125 o c -1.0 1.0 a standby supply current iccsb vi = vcc or gnd, vcc = 5.5v, io = 0ma 1, 2, 3 -55 o c ta +125 o c - 100 a operating supply current iccop vcc = 5.5v, g = gnd, (note 3), f = 1mhz, io = 0ma, vi = vcc or gnd 1, 2, 3 -55 o c ta +125 o c - 20 ma functional test ft vcc = 4.5v (note 6) 7, 8a, 8b -55 o c ta +125 o c- - table 2. hm-6617/883 ac electrical performance specifications device guaranteed and 100% tested parameter symbol (notes 1, 2, 4) conditions group a subgroups temperature limits hm-6617b/883 limits hm-6617/883 units min max min max address access time tavqv vcc = 4.5v and 5.5v (note 5) 9, 10, 11 -55 o c ta +125 o c - 105 - 140 ns output enable access time tglqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c- 40 - 50 ns chip enable access time telqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c - 90 - 120 ns address setup time tavel vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c15 - 20 - ns address hold time telax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c20 - 25 - ns chip enable low width teleh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c 95 - 120 - ns chip enable high width tehel vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c40 - 40 - ns hm-6617/883
4 read cycle time telel vcc = 4.5v and 5.5v 9, 10, 11 -55 o c ta +125 o c 136 - 160 - ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume transition time 5ns; input levels = 0.0v to 3.0v; timing reference levels = 1.5v; output load = 1ttl equiva- lent load and cl ? 50pf. 3. typical derating = 5ma/mhz increase in iccop. 4. all tests performed with p hardwired to vcc. 5. tavqv = telqv + tavel. 6. tested as follows: f = 1mhz, vih = 2.4v, vil = 0.8v, ioh = -1ma, iol = +1ma, voh 1.5v, vol 1.5v. table 3. hm-6617/883 ac and dc electrical performance specifications parameter symbol (notes 1, 2) conditions notes temperature limits hm-6617b/883 limits hm-6617/883 units min max min max input capacitance cin vcc = open, f = 1mhz, all measurements referenced to device gnd 2, 3 +25 o c-10-10pf vcc = open, f = 1mhz, all measurements referenced to device gnd 2, 4 +25 o c-12-12pf 2, 5 +25 o c-10-10pf i/o capacitance ci/o vcc = open, f = 1mhz, all measurements referenced to device gnd 2, 3 +25 o c-12-12pf vcc = open, f = 1mhz, all measurements referenced to device gnd 2, 4 +25 o c-14-14pf 2, 5 +25 o c-12-12pf chip enable time telqx vcc = 4.5v and 5.5v 2 -55 o c ta +125 o c5 - 5 - ns output enable time tglqx vcc = 4.5v and 5.5v 2 -55 o c ta +125 o c5 - 5 - ns chip disable time tehqz vcc = 4.5v and 5.5v 2 -55 o c ta +125 o c- 45 - 50 ns output disable time tghqz vcc = 4.5v and 5.5v 2 -55 o c ta +125 o c- 40 - 50 ns output high voltage voh2 vcc = 4.5v, io = 100 a 2 -55 o c ta +125 o c vcc- 1v - vcc- 1v -v notes: 1. all tests performed with p hardwired to vcc. 2. the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parameters are char- acterized upon initial design changes which would affect these characteristics. 3. applies to 0.600 inch sbdip device types only. 4. applies to 0.300 inch sbdip device types only. 5. applies to ceramic leadless chip carrier (clcc) device types only. table 2. hm-6617/883 ac electrical performance specifications (continued) device guaranteed and 100% tested parameter symbol (notes 1, 2, 4) conditions group a subgroups temperature limits hm-6617b/883 limits hm-6617/883 units min max min max hm-6617/883
5 table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100%/5004 1 final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a samples/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 groups c & d samples/5005 1, 7, 9 switching waveforms figure 1. read cycle test circuit figure 2. test circuit tavqv telel teleh tavel tehel telqx tghqz tehqz tglqx telqv tglqv telax addresses e g data 1.5v 1.5v 1.5v 1.5v 3.0v 0v 3.0v 0v 3.0v 0v t s 1.5v addresses valid data valid address valid 1.5v 1.5v output q0-q7 1.5v dut equivalent circuit 1.5v i ol i oh c l test head capacitance (note) note: hm-6617/883
6 burn-in circuits hm-6617/883 (.300 inch) sbdip hm-6617/883 (.600 inch) sbdip hm-6617/883 clcc notes: f0 = 100khz 10%. all resistors = 47k ? unless otherwise noted. vcc = 5.5v 0.05v. c = 0.01 f min. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 gnd a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 q7 q6 q5 q4 q3 vcc a8 a9 p g a10 e vcc/2 vcc/2 c 2.4k 2.4k 2.4k 2.4k 2.4k 2.4k 2.4k gnd vcc f7 f6 f3 f4 f5 f1 f2 f12 vcc f10 f0 f11 2.4k f8 f9 1 2 3 4 5 6 7 8 9 11 12 16 17 18 19 20 21 22 23 24 15 14 13 10 vcc f13 c f1 f12 gnd f11 f0 vcc/2 f7 f6 f3 f4 f5 f1 f2 f8 vcc vcc/2 q7 q6 q5 q4 q3 vcc a6 a5 p g a10 e gnd a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 27 28 29 26 25 24 23 3 2 1 4 32 31 30 5 6 7 8 11 10 9 16 17 18 19 20 14 15 22 21 12 13 nc nc nc nc nc nc nc nc f10 c vcc vcc f12 vcc/2 f1 f13 f0 f11 vcc/2 vcc/2 vcc/2 f7 f6 f3 f4 f5 f8 f9 hm-6617/883
7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or specifications at a ny time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to b e accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third p arties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its sub sidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 140 x 232 x 19 1mils metallization: type: si - al thickness: 11k ? 15k ? glassivation: type: sio 2 thickness: 7k ? 9k ? worst case current density: 1.7 x 10 5 a/cm 2 metallization mask layout hm-6617/883 a4 a5 a6 a7 vcc a8 a9 p g a10 e q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 hm-6617/883
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